RDO-WT: optimised Wallace Tree multiplier based FIR filter for signal processing applications

Digital Signal Processing (DSP) and communication applications utilise a Finite Impulse Response (FIR) filter which is key component for digital communication. Moreover, quality of signal is enhanced by FIR filter which is mostly employed by filtering applications. The execution speed of the FIR is...

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Bibliographic Details
Published inInternational journal of electronics Vol. 109; no. 10; pp. 1759 - 1780
Main Authors Malathi, L., Bharathi, A., Jayanthi, A. N.
Format Journal Article
LanguageEnglish
Published Abingdon Taylor & Francis 03.10.2022
Taylor & Francis LLC
Subjects
Algorithms
Critical path
Design optimization
Digital signal processing
error reduction
filter design
Filter design (mathematics)
FIR filters
Multipliers
noise removal
Red Deer Optimisation (RDO) algorithm
Signal processing
Signal quality
Simulation
Wallace Tree Multiplier
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Summary:Digital Signal Processing (DSP) and communication applications utilise a Finite Impulse Response (FIR) filter which is key component for digital communication. Moreover, quality of signal is enhanced by FIR filter which is mostly employed by filtering applications. The execution speed of the FIR is determined by multiplier's performance. Hardware resource utilisation and speed-up operations are some of the issues found in existing methods which are occurred due to a critical path in incomplete products. So, this can be improved by the proposed optimisation algorithm based multiplier. This research establishes the execution of FIR Filter design using Red Deer Optimisation (RDO) based Wallace Tree (WT) multiplier. By using the optimised WT multiplier, FIR filter is simulated to examine the area, delay, power and frequency for different tap FIR filter. Moreover, FIR filter with optimised WT is introduced to perform signal denoising application. Proposed multiplier design is simulated using Xilinx tool. Filtering simulation is done by using the publicly available database named as MIT-BIH database and the noise removal process is simulated using Matlab tool. The FIR filter designed with proposed multiplier provides delay around 1.373 ns and consumes 0.143 W as total power which is lesser than the existing methods.
ISSN:0020-7217
1362-3060
DOI:10.1080/00207217.2021.2001853