Design considerations for very-high-speed Si-bipolar IC's operating up to 50 Gb/s

• Published in: IEEE journal of solid-state circuits Vol. 31; no. 8; pp. 1076 - 1090
• Main Authors: Rein, H.-M., Moller, M.
• Format: Journal Article
• Language: English
• Published: IEEE 01.08.1996
• Subjects: Analog integrated circuits; Bonding; Circuit optimization; Digital circuits; Digital integrated circuits; High speed integrated circuits; Integrated circuit modeling; Optical design; Transistors; Wiring
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/4.508255

In this paper, design aspects of high-speed digital and analog IC's are discussed which allow the designer to exhaust the high-speed potential of advanced Si-bipolar technologies. Starting from the most promising circuit concepts and an adequate resistance level, the dimensions of the individual transistors in the IC's must be optimized very carefully using advanced transistor models. It is shown how the bond inductances can be favourably used to improve circuit performance and how the critical on-chip wiring must be taken into account. Moreover, special modeling aspects and ringing problems, caused by emitter followers, are discussed. An inexpensive mounting technique is presented which proved to be well suited up to 50 Gb/s, the highest data rate ever achieved in any IC technology. The suitability of the design aspects discussed is confirmed by measurements of digital circuits and broadband amplifiers developed for 10 and 40 Gb/s optical-fiber links.