VHDL behavioral ATPG and fault simulation of digital systems

• Published in: IEEE transactions on aerospace and electronic systems Vol. 34; no. 2; pp. 428 - 447
• Main Authors: Chen, C.-I.H., Noh, T.H.
• Format: Journal Article
• Language: English
• Published: IEEE 01.04.1998
• Subjects: Automatic test pattern generation; Circuit faults; Circuit simulation; Circuit synthesis; Circuit testing; Computational modeling; Design automation; Digital systems; Hardware design languages; Very large scale integration
• ISSN: 0018-9251; 1557-9603
• DOI: 10.1109/7.670325

Due to the increasing level of integration achieved by Very Large Scale Integrated (VLSI) technology, traditional gate-level fault simulation is becoming more complex, difficult, and costly. Furthermore, circuit designs are increasingly being developed through the use of powerful VLSI computer-aided design (CAD) synthesis tools which emphasize circuit descriptions using high-level representations of functional behavior, rather than physical architectures and layout. Behavior fault simulation applied to the top functional level models described using a hardware description language offers a very attractive alternative to these problems. A new way to simulate the behavioral fault models using the hardware description language (HDL), such as VHDL, is presented. Tests were generated by carrying out the behavioral fault simulation for a few circuit models. For comparison, a gate-level fault simulation on the equivalent circuit, produced via a synthesis tool, was used. The performance analysis shows that a very small number of test patterns generated by the behavioral automatic test pattern generation (ATPG)/fault simulation system detected around 98 percent of the testable gate-level faults that were detected by random test.