A speedup method of a high-speed direct-coupled Josephson logic gate

The switching mechanism of a direct-coupled Josephson logic gate, a four-junction logic gate, has been investigated. It was found that a high-speed input signal current is wasted in an input-output separation resistance (R/sub i/). A speedup method has been developed in which an inductance is connec...

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Bibliographic Details
Published inIEEE transactions on applied superconductivity Vol. 3; no. 1; pp. 2679 - 2682
Main Authors Aoyagi, M., Nakagawa, H., Kurosawa, I., Akoh, H., Takada, S.
Format Journal Article Conference Proceeding
LanguageEnglish
Published New York, NY IEEE 01.03.1993
Institute of Electrical and Electronics Engineers
Subjects
Applied sciences
Circuit properties
Circuits
Computer simulation
Critical current density
Delay effects
Delay estimation
Digital circuits
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Exact sciences and technology
Inductance
Josephson junctions
Laboratories
Logic gates
Switches
Logic circuit
Logic gate
Josephson junction
Fast circuit
High temperature superconductor
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Summary:The switching mechanism of a direct-coupled Josephson logic gate, a four-junction logic gate, has been investigated. It was found that a high-speed input signal current is wasted in an input-output separation resistance (R/sub i/). A speedup method has been developed in which an inductance is connected to (R/sub i/) in series. The value of the inductance was found to be five times larger than the effective inductance of the input junction. A speedup of 40% in the gate switching was demonstrated by a logic delay experiment using submicron NbN-MgO-NbN junction technology. The minimum logic delay of 3.0 ps/gate was obtained with fan-out 1.< >
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ISSN:1051-8223
1558-2515
DOI:10.1109/77.233978