A test structure advisor and a coupled, library-based test structure layout and testing environment

• Published in: IEEE transactions on semiconductor manufacturing Vol. 10; no. 3; pp. 370 - 383
• Main Authors: Kumar, M.V., Lukaszek, W., Plummer, J.D.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.08.1997; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Automatic testing; BiCMOS integrated circuits; Chip scale packaging; CMOS process; Computer science; control theory; systems; Control theory. Systems; Design engineering; Documentation; Exact sciences and technology; Process control. Computer integrated manufacturing; Productivity; Semiconductor device measurement; Software libraries; Software testing; Test method; Computer integrated manufacturing; System description; Fault diagnostic; Integrated circuit
• ISSN: 0894-6507; 1558-2345
• DOI: 10.1109/66.618210

A new test chip design environment, based on commercial tools, containing a test structure advisor and a coupled, library-based layout and testing environment has been developed that dramatically increases productivity. The test structure advisor analyzes cross sections of devices to recommend a comprehensive list of diagnostic and parametric test structures. These test structures can then be retrieved from the libraries of parameterized structures, customized, and placed in a design to rapidly generate customized test chips. Coupling of the layout and test environments enables the automatic generation of the vast majority of the parametric test software. This environment, which has been used to design test chips for a low-power/low-voltage CMOS process, a BiCMOS trench process, and a TFT process, results in an estimated tenfold increase in productivity. In addition, the redesign of five modules of Stanford's existing BiCMOS test chip, using parameterized test structures, showed an 8/spl times/ improvement in layout time alone.