Evaluation and design of an ultra-reliable distributed architecture for fault tolerance

• Published in: IEEE transactions on reliability Vol. 39; no. 4; pp. 492 - 499
• Main Author: Walter, C.J.
• Format: Journal Article
• Language: English
• Published: IEEE 01.10.1990
• Subjects: Communication system control; Fault tolerance; Fault tolerant systems; Integrated circuit testing; Performance evaluation; Probability; Processor scheduling; Prototypes; Redundancy; System testing
• ISSN: 0018-9529; 1558-1721
• DOI: 10.1109/24.58727

The issues related to the experimental evaluation of an early conceptual prototype of the MAFT (multicomputer architecture for fault tolerance) architecture are discussed. A completely automated testing approach was designed to allow fault-injection experiments to be performed, including stuck-at and memory faults. Over 2000 injection tests were run and the system successfully tolerated all faults. Concurrent with the experimental evaluation, an analytic evaluation was carried out to determine if higher levels of reliability could be achieved. The lessons learned in the evaluation phase culminated in a new design of the MAFT architecture for applications needing ultrareliability. The design uses the concept of redundantly self-checking functions to address the rigid requirements proposed for a future generation of mission-critical avionics. The testing of three subsystems critical to the operation of the new MAFT is presented with close to 50-k test cycles performed over 51 different IC devices to verify the designs.< >