A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth

• Published in: IEEE journal of solid-state circuits Vol. 56; no. 12; pp. 3741 - 3755
• Main Authors: Qiu, Junjun, Sun, Zheng, Liu, Bangan, Wang, Wenqian, Xu, Dingxin, Herdian, Hans, Huang, Hongye, Zhang, Yuncheng, Wang, Yun, Pang, Jian, Liu, Hanli, Miyahara, Masaya, Shirane, Atsushi, Okada, Kenichi
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.12.2021; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: 32 kHz; Analog circuits; bang-bang phase detector (BBPD); BWloop; Calibration; Circuit design; CMOS; Co-design; comparator (CMP); constant-slope digital-to-time converter (DTC); Digital to analog conversion; Digital to analog converters; Digital-analog conversion; digital-to-analog converter (DAC); Electric potential; fractional-<italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">N; frequency synthesizer; inductor–capacitor (LC) oscillator (DCO); Jitter; Lookup tables; mixed analog-digital circuit; over-sampling phase-locked loop (OSPLL); Oversampling; Phase detectors; Phase locked loops; Phase noise; Power consumption; Quantization (signal); reference construction; Reference signals; Signal resolution; Vibration; Voltage
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2021.3106514

In this article, a mixed-signal, 32-kHz reference-based 2.4-GHz fractional-<inline-formula> <tex-math notation="LaTeX">{N} </tex-math></inline-formula> over-sampling phase-locked loop (OSPLL) is proposed. Different from the conventional <inline-formula> <tex-math notation="LaTeX">1\times </tex-math></inline-formula> sampling PLL, which only uses zero-crossing timing information of the reference signal, the proposed OSPLL fully utilizes both the voltage and timing domain information of the reference signal and realizes oversampling ratio (OSR) times phase detection (PD) in one reference cycle. The proposed OSPLL employs the digital-to-analog converter (DAC) to construct the reference-like feedback signal in the voltage domain and utilizes the digital-to-time converter (DTC) to improve PD resolution in the time domain. The adaptive lookup table (LuT)-based calibration is proposed to generate the correct information for DAC and DTC control. A clocked passive comparator works as a bang-bang phase detector (BBPD) for the PLL control and LuTs' construction. The co-design of low-noise analog circuits and digital calibrations enables good jitter and spur performance. The proposed OSPLL is fabricated in 65-nm CMOS technology, with the core area of 0.58 mm 2 , and the power consumption is 4.97 mW with a 1-V power supply. It achieves 5.79-ps root-mean-square (rms) jitter in fractional-<inline-formula> <tex-math notation="LaTeX">{N} </tex-math></inline-formula> modes with the loop-bandwidth (BW loop ) of 200 kHz, corresponding to the figures of merit (FoMs) of −217.8 dB. The measured fractional spur is less than −36 dBc, and the reference spur is −78 dBc, respectively.