Using simulators to model transmitted variability in IC manufacturing

• Published in: IEEE transactions on semiconductor manufacturing Vol. 2; no. 3; pp. 82 - 93
• Main Authors: Sharifzadeh, S., Koehler, J.R., Owen, A.B., Shott, J.D.
• Format: Journal Article
• Language: English
• Published: IEEE 01.08.1989
• Subjects: Boron; CMOS process; Computational modeling; Design methodology; Fabrication; Implants; Integrated circuit modeling; Response surface methodology; Threshold voltage; Transconductance
• ISSN: 0894-6507; 1558-2345
• DOI: 10.1109/66.29674

The authors describe a response surface design methodology based on process and device simulations to estimate device variations due to changes in process input parameters from their designed values. The gradient of the simulated device characteristics is estimated directly and used to compute device sensitivities. This methodology was applied to Stanford's 2- mu m CMOS fabrication process. Threshold voltage, subthreshold slope, linear transconductance, and saturation current were picked as the target device characteristics for optimization. Five process parameters were examined: boron concentration in the wafer, phosphorous n-well implant dose, boron threshold adjust dose, gate oxidation temperature, and gate length. The methodology was shown to be successful for the exploration of device characteristic values as a function of process parameters, but success for the transmitted variability, because it depends on derivatives which tend to be less like polynomials than the functions themselves, is more limited. In the absence of a direct assessment of the derivative, response surface models fit to the simulator values can give a very misleading picture of the transmitted variability. Models used were quadratic models for Box-Cox transformed device characteristics.< >