2.1 dB noise figure 5.2 GHz CMOS low noise amplifier using wafer-level integrated passive device technology with a DC power consumption of 10 mW
This work presents an inductor with a high quality factor (Q) that is fabricated using wafer-level integrated passive device (IPD) technology and a 5.2 GHz differential low noise amplifier (DLNA) in a Taiwan semiconductor manufacturing company (TSMC(TM)) 0.18 µm complementary metal-oxide-semiconduct...
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Published in | IET microwaves, antennas & propagation Vol. 6; no. 11; pp. 1286 - 1290 |
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Main Authors | , , , |
Format | Journal Article |
Language | English |
Published |
Stevenage
Institution of Engineering and Technology
21.08.2012
The Institution of Engineering & Technology |
Subjects | |
Online Access | Get full text |
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Summary: | This work presents an inductor with a high quality factor (Q) that is fabricated using wafer-level integrated passive device (IPD) technology and a 5.2 GHz differential low noise amplifier (DLNA) in a Taiwan semiconductor manufacturing company (TSMC(TM)) 0.18 µm complementary metal-oxide-semiconductor (CMOS) process. The IPD inductors were stacked on top of a CMOS DLNA. The use of IPD inductors in the input matching network (IMN) is an efficient alternative to on-chip inductors for mass production. The performance of the DLNA with and without an IPD inductor is studied. The IPD CMOS-DLNA achieves a noise figure (NF) of 2.1 dB with a power consumption of 10 mW. The measured NF of the CMOS-IPD DLNA is 0.6 dB better than that of the typical CMOS DLNA at the same power consumption. The CMOS-IPD DLNA achieves the best figure of merit of any of the recently described 5-6 GHz CMOS LNAs. |
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Bibliography: | ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 23 |
ISSN: | 1751-8725 1751-8733 |
DOI: | 10.1049/iet-map.2011.0274 |