A Second-Order Noise-Shaping SAR ADC With Passive Integrator and Tri-Level Voting

• Published in: IEEE journal of solid-state circuits Vol. 54; no. 6; pp. 1636 - 1647
• Main Authors: Zhuang, Haoyu, Guo, Wenjuan, Liu, Jiaxin, Tang, He, Zhu, Zhangming, Chen, Long, Sun, Nan
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.06.2019; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analog-to-digital converter; Architecture; Capacitors; Clock generators; Clocks; CMOS; Computer architecture; Figure of merit; Gain; Generators; majority voting (MV); multi-phase non-overlapping clock generator; Noise; Noise reduction; Noise shaping; noise shaping (NS); Operational amplifiers; Oversampling; Scaling; successive approximation register; Switches; Transconductance; Transfer functions
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2019.2900150

This paper presents a low-power and scaling-friendly noise-shaping (NS) SAR ADC. Instead of using operational transconductance amplifiers that are power hungry and scaling unfriendly, the proposed architecture uses passive switches and capacitors to perform residue integration and realizes the path gains via transistor size ratios inside a multi-path dynamic comparator. The overall architecture is simple and robust. Since the noise transfer function is set by component ratios, it is insensitive to process, voltage, and temperature (PVT) variations. Besides the proposed architecture, this paper also presents two new circuit techniques. A tri-level voting scheme is proposed to reduce the comparator noise. It outperforms the majority voting technique by exploiting more information in the comparator output statistics and providing an extra decision level. A dynamic multi-phase clock generator is also proposed to guarantee non-overlapping and support an arbitrary number of phases. A prototype 9-bit NS-SAR ADC is fabricated in a 40-nm CMOS process. It consumes <inline-formula> <tex-math notation="LaTeX">143~\mu \text{W} </tex-math></inline-formula> at 1.1 V while operating at 8.4 MS/s. Taking advantage of the second-order NS, it achieves a peak SNDR of 78.4 dB over a bandwidth of 262 kHz at the oversampling ratio of 16, leading to an SNDR-based Schreier figure of merit (FoM) of 171 dB.