CONV-SRAM: An Energy-Efficient SRAM With In-Memory Dot-Product Computation for Low-Power Convolutional Neural Networks

• Published in: IEEE journal of solid-state circuits Vol. 54; no. 1; pp. 217 - 230
• Main Authors: Biswas, Avishek, Chandrakasan, Anantha P.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.01.2019; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analog computing; Analog to digital conversion; Analog to digital converters; Artificial neural networks; binary weights; Cloud computing; Computer architecture; Computer memory; Convolution; convolutional neural networks (CNNs); Data transfer (computers); dot-product; Edge computing; Energy conversion efficiency; Energy efficiency; energy-efficient SRAM; Feature extraction; in-memory computation; machine learning (ML); Neural networks; Object recognition; Random access memory; Static random access memory; Weight
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2018.2880918

This paper presents an energy-efficient static random access memory (SRAM) with embedded dot-product computation capability, for binary-weight convolutional neural networks. A 10T bit-cell-based SRAM array is used to store the 1-b filter weights. The array implements dot-product as a weighted average of the bitline voltages, which are proportional to the digital input values. Local integrating analog-to-digital converters compute the digital convolution outputs, corresponding to each filter. We have successfully demonstrated functionality (>98% accuracy) with the 10 000 test images in the MNIST hand-written digit recognition data set, using 6-b inputs/outputs. Compared to conventional full-digital implementations using small bitwidths, we achieve similar or better energy efficiency, by reducing data transfer, due to the highly parallel in-memory analog computations.