FMER: An Energy-Efficient Error Recovery Methodology for SRAM-Based FPGA Designs

• Published in: IEEE transactions on aerospace and electronic systems Vol. 54; no. 6; pp. 2695 - 2712
• Main Authors: Agiakatsikas, Dimitris, Cetin, Ediz, Diessel, Oliver
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.12.2018; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Availability; configuration memory (CM) error recovery (ER) techniques; Configurations; Energy budget; Energy management; Energy recovery; Erbium; Error recovery; Errors; fault tolerance; Field programmable gate arrays; Missions; Modular design; Pins; Power consumption; Power management; radiation-induced errors; Random access memory; Reliability; Reliability engineering; single event upsets (SEUs); Soft errors; SRAM-based FPGAs; Static random access memory; Tunneling magnetoresistance; Washing
• ISSN: 0018-9251; 1557-9603
• DOI: 10.1109/TAES.2018.2828201

This paper introduces frame- and module-based configuration memory error recovery (FMER), that is, a FMER technique targeting triple modular redundant (TMR) designs that are realized on SRAM-based FPGAs. Module-based configuration memory (CM) error recovery (MER) is used to reconfigure on demand the CM of faulty TMR modules, whereas the remaining CM of the device recovers from soft errors with periodic scrubbing. We derive reliability, availability, and power consumption models of TMR designs that incorporate FMER, MER, blind scrubbing, and no recovery at all, and show that FMER is particularly beneficial for missions that require high reliability or availability subject to a low-energy budget.