A High PSRR, Low Ripple, Temperature-Compensated, 10-μA-Class Digital LDO Based on Current-Source Power-FETs for a Sub-mW SoC

State-of-the-art digital low-dropout regulators (LDOs) have shown competitive dynamic load regulation at a scaled output capacitor size. However, achieving high power-supply-rejection-ratio (PSRR) and small output ripple in a digital LDO remains a challenge. We present a digital LDO targeted for a s...

Full description

Saved in:
Bibliographic Details
Published inIEEE solid-state circuits letters Vol. 4; pp. 88 - 91
Main Authors Kim, Sung Justin, Chang, Soo Bong, Seok, Mingoo
Format Journal Article
LanguageEnglish
Published Piscataway IEEE 2021
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Current sources
Digital low-dropout regulator (LDO)
dynamic load regulation
Dynamic loads
Dynamic stability
Field effect transistors
Generators
MOS devices
output voltage ripple
power-supply-rejection-ratio (PSRR)
Regulation
Regulators
Ripples
Solid state circuits
Switches
System on chip
temperature coefficient (TC)
Temperature measurement
Online AccessGet full text

Cover

More Information
Summary:State-of-the-art digital low-dropout regulators (LDOs) have shown competitive dynamic load regulation at a scaled output capacitor size. However, achieving high power-supply-rejection-ratio (PSRR) and small output ripple in a digital LDO remains a challenge. We present a digital LDO targeted for a sub-mW system-on-a-chip, featuring current-source-based power-FETs and hybrid event-/time-driven digital control. The prototype in 65-nm achieves -32-dB PSRR with 126-nA quiescent current, 10.9-mV worst-case output ripple, 58.1 ppm/°C temperature stability, and 0.15-pF dynamic load regulation figure-of-merit (pF-FoM).
ISSN:2573-9603
2573-9603
DOI:10.1109/LSSC.2021.3070556