Test point insertion methods to reduce the number of ATPG patterns

• Published in: Electronics & communications in Japan. Part 2, Electronics Vol. 89; no. 5; pp. 54 - 68
• Main Authors: Yoshimura, Masayoshi, Hosokawa, Toshinori, Ohta, Misuyasu
• Format: Journal Article
• Language: English
• Published: Hoboken Wiley Subscription Services, Inc., A Wiley Company 01.05.2006
• Subjects: full scan design; number of ATPG patterns; test execution time; test point insertion method
• ISSN: 8756-663X; 1520-6432
• DOI: 10.1002/ecjb.20267

The increasing density of LSI chip circuits is causing the execution time of tests based on the full‐scan design method to become problematical. In this paper, the authors propose a method of reducing the number of ATPG patterns for a full‐scan designed LSI chip by inserting test points. To reduce the number of ATPG patterns, they proposed a test point insertion algorithm based on the improved fault detection probability and a test point insertion algorithm based on the improved value assignment probability. When the authors applied the proposed methods to several actual LSI chips, they were able to reduce the number of ATPG patterns by 48% to 78% compared with the conventional full‐scan design by adding test points equivalent to 0.4% to 2.2% of the total number of flip‐flops in the LSI chip. © 2006 Wiley Periodicals, Inc. Electron Comm Jpn Pt 2, 89(5): 54–68, 2006; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjb.20267