An automatic temperature compensation of internal sense ground for subquarter micron DRAM's

This paper describes DRAM array driving techniques and the parameter scaling techniques for low voltage operation using the boosted sense ground (BSG) scheme and further improved methods. Temperature compensation and adjustable internal voltage levels maintain a small subthreshold leakage current fo...

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Published inIEEE journal of solid-state circuits Vol. 30; no. 4; pp. 471 - 479
Main Authors Ooishi, T., Komiya, Y., Hamade, K., Asakura, M., Yasuda, K., Furutani, K., Hidaka, H., Miyamoto, H., Ozaki, H.
Format Journal Article Conference Proceeding
LanguageEnglish
Published New York, NY IEEE 01.04.1995
Institute of Electrical and Electronics Engineers
Subjects
Applied sciences
Circuits
Decoding
Electronics
Exact sciences and technology
Integrated circuits
Integrated circuits by function (including memories and processors)
Land surface temperature
Leakage current
Low voltage
Power system reliability
Random access memory
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Subthreshold current
Temperature sensors
Threshold voltage
Waveform
Scanning electron microscopy
VLSI circuit
Function block diagram
Cross section
Dynamical storage
Temperature effect
Theoretical study
Adjustable
Operation study
Low voltage
Experimental result
Scale parameter
Electric scheme
Subthreshold
Numerical simulation
Leakage current
Semiconductor storage
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Summary:This paper describes DRAM array driving techniques and the parameter scaling techniques for low voltage operation using the boosted sense ground (BSG) scheme and further improved methods. Temperature compensation and adjustable internal voltage levels maintain a small subthreshold leakage current for a memory cell transistor (MC-Tr), and a distributed BSG (DBSG) scheme and a column decoded sensing (CDS) scheme achieve the effective scaling. These schemes can set the DRAM array free from the leakage current problem and the influence of temperature variations. Therefore, parameters for the MC-Tr, threshold voltage (V/sub th/), and the boosted voltage for the gate bias can be scaled down, and it is possible to determine the V/sub th/ of the MC-Tr simply (0.45 V at K=0.4) for the satisfaction of the small leakage current, for high speed and stable operation, and for high reliability (V/sub PP/ is below 2 V/sub CC/). They are applicable to subquarter micron DRAM's of 256 Mb and more.< >
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0018-9200
1558-173X
DOI:10.1109/4.375968