A 22 nm 15-Core Enterprise Xeon® Processor Family

This paper describes a 4.3B transistors, 15-cores, 30-threads enterprise Xeon® processor with a 37.5 MB shared L3 cache implemented in a 22 nm 9M Hi-K metal gate tri-gate process. A modular floorplan methodology enables easy chops to 10 and 6 cores. Multiple clock and voltage domains are used to red...

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Bibliographic Details
Published inIEEE journal of solid-state circuits Vol. 50; no. 1; pp. 35 - 48
Main Authors Rusu, Stefan, Muljono, Harry, Ayers, David, Tam, Simon, Wei Chen, Martin, Aaron, Shenggao Li, Vora, Sujal, Varada, Raj, Wang, Eddie
Format Journal Article
LanguageEnglish
Published IEEE 01.01.2015
Subjects
22 nm process technology
Arrays
Bandwidth
Circuit design
clock distribution
Clocks
computer architecture
core recovery
leakage reduction
Metals
microprocessor
Phase locked loops
Servers
Transistors
voltage domains
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Summary:This paper describes a 4.3B transistors, 15-cores, 30-threads enterprise Xeon® processor with a 37.5 MB shared L3 cache implemented in a 22 nm 9M Hi-K metal gate tri-gate process. A modular floorplan methodology enables easy chops to 10 and 6 cores. Multiple clock and voltage domains are used to reduce power consumption. The clock distribution uses a single PLL per column to save power and minimize deskew crossing points. Integrated PCIe Gen3 and Quick Path Interconnect® (QPI) ports operate at 8GT/s. The 4-channel memory interface supports both 1866 MT/s DDR3 and a new memory buffer interface running at 2667 MT/s on the same pins. The core, cache and I/O recovery techniques improve manufacturing yields and enable multiple product flavors from the same silicon die.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2014.2368933