1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS

• Published in: IEEE journal of solid-state circuits Vol. 30; no. 8; pp. 847 - 854
• Main Authors: Mutoh, S., Douseki, T., Matsuya, Y., Aoki, T., Shigematsu, S., Yamada, J.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.08.1995; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; CMOS digital integrated circuits; CMOS technology; Design. Technologies. Operation analysis. Testing; Digital circuits; Electronics; Exact sciences and technology; Integrated circuits; Large scale integration; Leakage current; Logic gates; Low voltage; Power supplies; Propagation delay; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Sleep; Integrated circuits; Portable equipment; Experimental study; Complementary MOS technology; Digital circuits; LSI circuits
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/4.400426

1-V power supply high-speed low-power digital circuit technology with 0.5-/spl mu/m multithreshold-voltage CMOS (MTCMOS) is proposed. This technology features both low-threshold voltage and high-threshold voltage MOSFET's in a single LSI. The low-threshold voltage MOSFET's enhance speed performance at a low supply voltage of 1 V or less, while the high-threshold voltage MOSFET's suppress the stand-by leakage current during the sleep period. This technology has brought about logic gate characteristics of a 1.7-ns propagation delay time and 0.3-/spl mu/W/MHz/gate power dissipation with a standard load. In addition, an MTCMOS standard cell library has been developed so that conventional CAD tools can be used to lay out low-voltage LSI's. To demonstrate MTCMOS's effectiveness, a PLL LSI based on standard cells was designed as a carrying vehicle. 18-MHz operation at 1 V was achieved using a 0.5-/spl mu/m CMOS process.< >