Feasibility of Cascadable Plasmonic Full Adder

• Published in: IEEE photonics journal Vol. 11; no. 4; pp. 1 - 12
• Main Authors: Fukuda, Mitsuo, Watanabe, Ryo, Tonooka, Yuta, Ota, Masashi
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 01.08.2019; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Adders; Adding circuits; Computer simulation; Finite difference method; full adder; Interference; Logic; logic circuit; Logic circuits; Metal oxides; Optical waveguides; plasmonic waveguide; Plasmons; Silicon dioxide; Stray light; Surface plasmon polariton; Time domain analysis; Waveguides
• ISSN: 1943-0655; 1943-0655; 1943-0647
• DOI: 10.1109/JPHOT.2019.2932262

The concept and configuration of a plasmonic cascadable full adder are proposed, whose logic operation is carried out by interference of surface plasmons and whose circuits are formed only with single- and multiple-mode plasmonic waveguides. This full adder is fabricated by patterning a SiO 2 film deposited on a metal film using complementary metal-oxide-semiconductor-compatible processes except for the material of metal. The redundant surface plasmons present after interference are drained from the waveguides by forming radiation ports, and metal bumps are formed in the circuits to prevent stray light recoupling with the waveguides. The logic operation of the circuits is numerically confirmed by the three-dimensional finite-difference time domain method, and the difference in surface plasmon intensity between logic level "0" and "1" is numerically estimated to be 1.5 dB even for the worst case. These simulations were experimentally confirmed for some input signal patterns using scanning near-field microscopy, and the surface plasmon intensity distributions monitored coincide well with those simulated.