Future system-on-silicon LSI chips
The development of system-on-silicon large-scale integration (LSI) devices has significantly influenced the demand for higher wiring connectivity within LSI chips. Currently, increasing the number of metal layers in a multilevel metallization as the device size decreases increases wiring connectivit...
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| Published in | IEEE MICRO Vol. 18; no. 4; pp. 17 - 22 |
|---|---|
| Main Authors | , , , , , |
| Format | Journal Article |
| Language | English |
| Published |
Los Alamitos
IEEE
01.07.1998
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subjects | |
| Online Access | Get full text |
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| Abstract | The development of system-on-silicon large-scale integration (LSI) devices has significantly influenced the demand for higher wiring connectivity within LSI chips. Currently, increasing the number of metal layers in a multilevel metallization as the device size decreases increases wiring connectivity. In the future, however, designers will have difficulty catching up with the rising demand for higher wiring connectivity by merely increasing the number of metal layers. We propose a new three-dimensional integration technology to overcome future wiring connectivity crises. In our solution, several vertically stacked chip layers in 3D LSI chips or 3D multichip modules (MCMs) are fabricated using our new integration technology. More than 10/sup 5/ interconnections per chip form in a vertical direction in these 3D LSI chips or 3D MCMs. Consequently, we can dramatically increase wiring connectivity while reducing the number of long interconnections. |
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| AbstractList | A new three-dimensional (3D) integration technology is proposed to overcome future wiring connectivity crises. In this new technology, several vertically stacked chip layers in 3D large-scale integration (LSI) chips or 3D multichip modules (MCMs) are fabricated. Use of this technology can dramatically increase wiring connectivity while reducing the number of long interconnections. The development of system-on-silicon large-scale integration (LSI) devices has significantly influenced the demand for higher wiring connectivity within LSI chips. Currently, increasing the number of metal layers in a multilevel metallization as the device size decreases increases wiring connectivity. In the future, however, designers will have difficulty catching up with the rising demand for higher wiring connectivity by merely increasing the number of metal layers. We propose a new three-dimensional integration technology to overcome future wiring connectivity crises. In our solution, several vertically stacked chip layers in 3D LSI chips or 3D multichip modules (MCMs) are fabricated using our new integration technology. More than 10/sup 5/ interconnections per chip form in a vertical direction in these 3D LSI chips or 3D MCMs. Consequently, we can dramatically increase wiring connectivity while reducing the number of long interconnections. The development of system-on-silicon large-scale integration (LSI) devices has significantly influenced the demand for higher wiring connectivity within LSI chips. Currently, increasing the number of metal layers in a multilevel metallization as the device size decreases increases wiring connectivity. In the future, however, designers will have difficulty catching up with the rising demand for higher wiring connectivity by merely increasing the number of metal layers. We propose a new three-dimensional integration technology to overcome future wiring connectivity crises. In our solution, several vertically stacked chip layers in 3D LSI chips or 3D multichip modules (MCMs) are fabricated using our new integration technology. More than 10(5) interconnections per chip form in a vertical direction in these 3D LSI chips or 3D MCMs. Consequently, we can dramatically increase wiring connectivity while reducing the number of long interconnections By vertically stacking and gluing several large-scale integration wafers together, Koyanagi et al have created a new 3D-integration technology that also furthers chip-on-chip packaging technology. |
| Author | Koyanagi, M. Kurino, H. Kang Wook Lee Itani, H. Sakuma, K. Miyakawa, N. |
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| Cites_doi | 10.1177/1045389X9600700316 10.1109/ICISS.1997.630262 10.1109/ASPDAC.1998.669491 |
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| SubjectTerms | Circuit testing Image sensors Integrated circuit interconnections Integration Large scale integration Latches Pipelines Random access memory Real time systems Semiconductors Sensor arrays Signal processing Technology |
| Title | Future system-on-silicon LSI chips |
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