Future system-on-silicon LSI chips

• Published in: IEEE MICRO Vol. 18; no. 4; pp. 17 - 22
• Main Authors: Koyanagi, M., Kurino, H., Kang Wook Lee, Sakuma, K., Miyakawa, N., Itani, H.
• Format: Journal Article
• Language: English
• Published: Los Alamitos IEEE 01.07.1998; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Circuit testing; Image sensors; Integrated circuit interconnections; Integration; Large scale integration; Latches; Pipelines; Random access memory; Real time systems; Semiconductors; Sensor arrays; Signal processing; Technology
• ISSN: 0272-1732; 1937-4143
• DOI: 10.1109/40.710867

The development of system-on-silicon large-scale integration (LSI) devices has significantly influenced the demand for higher wiring connectivity within LSI chips. Currently, increasing the number of metal layers in a multilevel metallization as the device size decreases increases wiring connectivity. In the future, however, designers will have difficulty catching up with the rising demand for higher wiring connectivity by merely increasing the number of metal layers. We propose a new three-dimensional integration technology to overcome future wiring connectivity crises. In our solution, several vertically stacked chip layers in 3D LSI chips or 3D multichip modules (MCMs) are fabricated using our new integration technology. More than 10/sup 5/ interconnections per chip form in a vertical direction in these 3D LSI chips or 3D MCMs. Consequently, we can dramatically increase wiring connectivity while reducing the number of long interconnections.