A 4-32 Gb/s Bidirectional Link With 3-Tap FFE/6-Tap DFE and Collaborative CDR in 22 nm CMOS

• Published in: IEEE journal of solid-state circuits Vol. 49; no. 12; pp. 3079 - 3090
• Main Authors: Musah, Tawfiq, Jaussi, James, Balamurugan, Ganesh, Hyvonen, Sami, Hsueh, Tzu-Chien, Keskin, Gokce, Shekhar, Sudip, Kennedy, Joseph, Sen, Shreyas, Inti, Rajesh, Mansuri, Mozhgan, Leddige, Michael, Horine, Bryce, Roberts, Clark, Mooney, Randy, Casper, Bryan
• Format: Journal Article
• Language: English
• Published: IEEE 01.12.2014
• Subjects: Active inductor CTLE; bidirectional link; Clocks; CMOS integrated circuits; Collaboration; collaborative CDR; conditional phase detection; Decision feedback equalizers; decision-feedback equalizer (DFE); Phase detection; phase error decimation; Receivers; regulated CMOS clocking; source-series terminated (SST) driver; Timing
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2014.2348556

This paper details the design of an 8-lane bidirectional link for both within-the-box and external communications in 22 nm CMOS technology. A low profile connector with a high density cable assembly ensure a data rate of up to 32 Gb/s per lane while maintaining channel loss below 25 dB. Channel equalization is performed by a combination of a 3-tap feed-forward equalizer (FFE), single-stage continuous-time linear equalizer (CTLE) and a 6-tap decision-feedback equalizer (DFE). Collaborative timing recovery is used to enable lane characterization without degrading jitter performance. Phase error decimation, with a conditional phase detection scheme, is used to reduce the DFE complexity by 50%. Power consumption over a wide range of data rates from 4 to 32 Gb/s is reduced by using regulated CMOS clocking with lane bundling, low swing transmitter with a source-series terminated (SST) driver and a highly reconfigurable receiver with an active inductor CTLE. At a lane data rate of 32 Gb/s, over a 0.5 m cable with 16 dB of loss, a transceiver lane consumes 205 mW from a 1.07 V supply. The power scales down to 26 mW from a 0.72 V supply at 8 Gb/s, when transmitting over a channel with 8 dB loss. The active silicon area per lane is 0.079 mm 2 .