Sealing Bump With Bottom-Up Cu TSV Plating Fabrication in 3-D Integration Scheme

A sealing bump approach for the simplification of the conventional bottom-up copper through-silicon via (TSV) plating process flow is developed to reduce the process steps and increase the throughput without sacrificing the structure integrity and electrical performance. In this approach, TSV and bu...

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Bibliographic Details
Published inIEEE electron device letters Vol. 34; no. 5; pp. 671 - 673
Main Authors CHIANG, Cheng-Hao, KUO, Li-Min, HU, Yu-Chen, HUANG, Wen-Chun, KO, Cheng-Ta, CHEN, Kuan-Neng
Format Journal Article
LanguageEnglish
Published New York, NY IEEE 01.05.2013
Institute of Electrical and Electronics Engineers
Subjects
3-D integration
Applied sciences
bottom-up plating
Current measurement
Design. Technologies. Operation analysis. Testing
Electrical resistance measurement
Electronics
Exact sciences and technology
Fabrication
Integrated circuits
Metals
Periodic structures
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Silicon
through-silicon via (TSV)
Through-silicon vias
bottom-up plating
Three dimensional structure
Interconnection
Integrated circuit
Silicon
Copper
Sealing
through-silicon via (TSV)
Electrical characteristic
Via hole
3-D integration
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Summary:A sealing bump approach for the simplification of the conventional bottom-up copper through-silicon via (TSV) plating process flow is developed to reduce the process steps and increase the throughput without sacrificing the structure integrity and electrical performance. In this approach, TSV and bump formation can be achieved simultaneously through the bottom-up plating. Results from the analysis reveal excellent electrical characteristics and quality examination, which indicate that the proposed approach may be a good candidate for the TSV fabrication in 3-D integration.
ISSN:0741-3106
1558-0563
DOI:10.1109/LED.2013.2250249