Loop-parameter optimization of a PLL for a low-jitter 2.5-Gb/s one-chip optical receiver IC with 1: 8 DEMUX

• Published in: IEEE journal of solid-state circuits Vol. 37; no. 1; pp. 38 - 50
• Main Authors: Kishine, K., Ishii, K., Ichino, H.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.01.2002; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Amplifiers; Character generation; Circuit design; Constraining; Damping; Electric potential; Frequency; Integrated circuits; Jitter; Optical amplifiers; Optical filters; Optimization; Optimization methods; Phase locked loops; Specifications; Voltage; Wide area networks
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/4.974544

A loop parameter optimization method for a phase-locked loop (PLL) used in wide area networks (WANs) is proposed as a technique for achieving good jitter characteristics. It is shown that the jitter characteristics of the PLL, especially jitter transfer and jitter generation, depend strongly on the key parameter /spl zeta//spl omega//sub n/ (/spl zeta/ is a damping factor and /spl omega//sub n/ is the natural angular frequency of the PLL), and that the optimization focusing on the /spl omega//sub n/ dependence of the jitter characteristics make it possible to comprehensively determine loop parameters and loop filter constants for a PLL that will fully comply with ITU-T jitter specifications. Using the optimization method with the low-jitter circuit design technique, a low-jitter and low-power 2.5-Gb/s optical receiver IC integrated with a limiting amplifier, clock and data recovery (CDR), and demultiplexer (DEMUX) is fabricated using 0.5-/spl mu/m Si bipolar technology (f/sub T/ = 40 GHz). The jitter characteristics of the IC meet all three types of jitter specifications given in ITU-T recommendation G.783. In particular, the measured jitter generation is 3.2 ps rms, which is lower than that of an IC integrated with only a CDR in our previous work. In addition, the pull-in range of the PLL is 50 MHz and the power consumption of the IC is only 0.68 W (limiting amplifier: 0.2 W, CDR (PLL): 0.3 W, DEMUX: 0.18 W) at a supply voltage of -3.3 V and only 0.35 W at a supply voltage of -2.5 V (without output buffers).