Modeling the Operation of Charge Trap Flash Memory-Part II: Understanding the ISPP Curve With a Semianalytical Model

• Published in: IEEE transactions on electron devices Vol. 71; no. 1; pp. 554 - 559
• Main Authors: Verreck, Devin, Schanovsky, Franz, Arreghini, Antonio, Van den Bosch, Geert, Stanojevic, Zlatan, Karner, Markus, Rosmeulen, Maarten
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.01.2024; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: 3-D nand; Computational efficiency; Computational modeling; Computing costs; Current density; flash memory; Flash memory (computers); incremental step pulse programming (ISPP); Logic gates; Mathematical models; modeling; Numerical models; Programming; Silicon; silicon-oxide-nitride-oxide-silicon (SONOS); SONOS devices; VNAND
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2023.3339112

Flash memory with a charge trap layer (CTL), also known as silicon-oxide-nitride-oxide-silicon (SONOS), is the most common type in production, yet there is a lack of consensus on the physical modeling of its operation. In Part I, we therefore proposed a full TCAD model based on an energy relaxation approach and showed that it captures experimentally observed memory operation. This numerical model, however, comes with considerable complexity and computational cost. In Part II, we therefore construct a semianalytical model based on similar physical assumptions, called Pheido, to be as simple as possible. We first derive the model equations based on a balance of current densities, detailing the approximations made. We then use Pheido to analyze the various regimes of an experimental incremental step pulse programming (ISPP) curve and compare it to the full TCAD model derived in Part I. Finally, we investigate the impact of material and structural cell parameters on the ISPP curve, illustrating how the Pheido model offers wide utility at low computational cost.