Flexible elliptic curve cryptography coprocessor using scalable finite field arithmetic blocks on FPGAs

• Published in: Microprocessors and microsystems Vol. 63; pp. 182 - 189
• Main Authors: Loi, K.C. Cinnati, Ko, Seok-Bum
• Format: Journal Article
• Language: English
• Published: Kidlington Elsevier B.V 01.11.2018; Elsevier BV
• Subjects: Arithmetic; Coprocessors; Cryptography; Dependence; Elliptic curve cryptography (ECC); Elliptic functions; Encryption; Field programmable gate array (FPGA); Field programmable gate arrays; Finite element analysis; Finite field arithmetic; Mathematics; NIST; Performance enhancement; Protocol (computers); Scalable ECC coprocessor; Xilinx XtremeDSP; NIST; Scalable ECC coprocessor; Field programmable gate array (FPGA); Finite field arithmetic; Xilinx XtremeDSP; Elliptic curve cryptography (ECC)
• ISSN: 0141-9331; 1872-9436
• DOI: 10.1016/j.micpro.2018.09.003

The increasing dependency of modern day information transferred over the network demands an increasing need of efficient implementations of security protocols on server and client devices to process the encryption and decryption of messages. This paper presents the design of an efficient scalable and unified Elliptic Curve Cryptography (ECC) coprocessor that takes advantage of the DSP48E slices on Xilinx FPGAs. The proposed coprocessor is able to evaluate the elliptic curve point multiplication (ECPM) for all 15 curves recommended by the National Institute of Standards and Technology (NIST). The DSP48E slices available in Xilinx FPGAs improve the performance of the coprocessor and provide the ability to evaluate dual-field arithmetic. The coprocessor has been implemented on a Xilinx Virtex-5 FPGA and it requires 4244 registers, 8316 LUTs, 2291 slices, 5 BRAMs and 25 DSP48E slices. It can evaluate the ECPM between 0.857 ms and 9.662 ms for prime curves and between 0.239 ms and 4.523 ms for binary curves. This paper also proposes a set of scalable finite field arithmetic blocks that can be programmed to implement different ECPM algorithms. In comparison with other ECC coprocessors in the current literature, the proposed design is very competitive in terms of timing performance and hardware resource utilization, while combining the scalability and dual-field features that are not available in other designs.