SiGe clock and data recovery IC with linear-type PLL for 10-Gb/s SONET application

• Published in: IEEE journal of solid-state circuits Vol. 35; no. 9; pp. 1353 - 1359
• Main Authors: Greshishchev, Y.M., Schvan, P.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.09.2000; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Charge pumps; Clocks; Detectors; Germanium silicon alloys; Integrated circuit technology; Jitter; Phase detection; Phase locked loops; Silicon germanium; Voltage-controlled oscillators
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/4.868047

An integrated 10 Gb/s clock and data recovery (CDR) circuit is fabricated using SiGe technology, It consists of a linear-type phase-locked loop (PLL) based on a single-edge version of the Hogge phase detector, a LC-tank voltage-controlled oscillator (VCO) and a tri-state charge pump. A PLL equivalent model and design method to meet SONET jitter requirements are presented. The CDR was tested at 9.529 GB/s in full operation and up to 13.25 Gb/s in data recovery mode. Sensitivity is 14 mV/sub pp/ at a bit error rate (BER)=10/sup -9/. The measured recovered clock jitter is less than 1 ps RMS. The IC dissipates 1.5 W with a -5 V power supply.