Partial product addition in Vedic design-ripple carry adder design fir filter architecture for electro cardiogram (ECG) signal de-noising application

• Published in: Microprocessors and microsystems Vol. 76; p. 103113
• Main Authors: Padmavathy, T.V., Saravanan, S., Vimalkumar, M.N.
• Format: Journal Article
• Language: English
• Published: Kidlington Elsevier B.V 01.07.2020; Elsevier BV
• Subjects: 8-bit multiplier; Adding circuits; Architecture; Bit error rate; Carry look ahead adder; Circuit design; Echocardiography; Electro cardiogram (ECG); Finite Impulse Response (FIR); FIR filters; Integrated circuits; Noise reduction; Signal de- noising; Signal processing; Signal to noise ratio; Vedic design; Vedic design; Finite Impulse Response (FIR); 8-bit multiplier; Signal de- noising; Carry look ahead adder; Electro cardiogram (ECG)
• ISSN: 0141-9331; 1872-9436
• DOI: 10.1016/j.micpro.2020.103113

Design of adder plays a major role in deciding overall performance of system as it is a major building block through generations of design in an innovative design of circuits. In VLSI system and signal processing field applications, various versions of adders are utilized. In applications of signal processing, in recent days, major role is contributed by Finite Impulse Response (FIR) filter. Various authors and papers described its design in a several ways. With the design of effective multiplier, signal denoising application was not explained by any of the existing works. For the generation of partial products, 8-bit multiplier based on a Vedic Mathematics –UrdhvaTiryagbhyam sutra- is proposed in this work. In Vedic multiplier, carry skip method is used for realizing addition of partial product. Four Vedic multipliers of 4 × 4 size are used for designing 8-bit multiplier. Carry skip and UrdhvaTiryagbhyam methods are used for this design. For addition of partial product, this multiplier is designed. Ripple carry adder's logic levels are modified for adding these Vedic multiplier's output. Powerful elimination of ECG noise can be done using this proposed fast FIR filter. In applications of healthcare and biomedical field, they are used. In Vedic design, Ripple Carry Adder (RCA) is used for carrying out partial product addition. Operation of FIR filter with Electro Cardiogram (ECG) signal is done by proposing architecture of FIR filter. It is termed as PPAVD-RCA-FIR and used in de-noising applications. From de-noised signal, Signal to Noise Ratio (SNR), Bit Error Rate (BER) and Mean Square Error (MSE) are computed, which are used for evaluating the performances. When compared with general Vedic multiplier, speed of the proposed design is increased about 13.65% as shown by results.