Single-event phenomena in GaAs devices and circuits

• Published in: IEEE transactions on nuclear science Vol. 43; no. 2; pp. 628 - 644
• Main Authors: McMorrow, D., Weatherford, T.R., Buchner, S., Knudson, A.R., Melinger, J.S., Lan Hu Tran, Campbell, A.B.
• Format: Journal Article
• Language: English
• Published: IEEE 01.04.1996
• Subjects: Circuit topology; Gallium arsenide; Heterojunction bipolar transistors; Integrated circuit technology; Isolation technology; Logic circuits; Logic devices; Single event upset; Space technology
• ISSN: 0018-9499; 1558-1578
• DOI: 10.1109/23.490906

The single-event upset (SEU) characteristics of GaAs devices and circuits are reviewed. GaAs FET-based integrated circuits (ICs) are susceptible to upsets from both cosmic-ray heavy ions and protons trapped in the Earth's radiation belts. The origin of the SEU sensitivity of GaAs ICs is discussed in terms of both device-level and circuit-level considerations. At the device level, efficient charge-enhancement mechanisms through which more charge can be collected than is deposited by the ion have a significant negative impact on the SEU characteristics of GaAs ICs. At the circuit level, different GaAs digital logic topologies exhibit different levels of sensitivity to SEU because of variations in parameters, including logic levels, capacitances, and the degree of gate or peripheral isolation. The operational and SEU characteristics of several different GaAs logic families are discussed. Recent advances in materials and processing that provide possible solutions to the SEU problem are addressed.