A novel low temperature integration of hybrid CMOS devices on flexible substrates
In this work we demonstrate a novel integration approach to fabricate CMOS circuits on plastic substrates (poly-ethylene naphthalate, PEN). We use pentacene and amorphous silicon (a-Si:H) thin-film transistors (TFTs) as p-channel and n-channel devices, respectively. The maximum processing temperatur...
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| Published in | Organic electronics Vol. 10; no. 7; pp. 1217 - 1222 |
|---|---|
| Main Authors | , , , , , , , |
| Format | Journal Article |
| Language | English |
| Published |
Amsterdam
Elsevier B.V
01.11.2009
Elsevier |
| Subjects | |
| Online Access | Get full text |
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| Abstract | In this work we demonstrate a novel integration approach to fabricate CMOS circuits on plastic substrates (poly-ethylene naphthalate, PEN). We use pentacene and amorphous silicon (a-Si:H) thin-film transistors (TFTs) as p-channel and n-channel devices, respectively. The maximum processing temperature for n-channel TFTs is 180
°C and 120
°C for the p-channel TFTs. CMOS circuits demonstrated in this work include inverters, NAND, and NOR gates. Carrier mobilities for nMOS and pMOS after the CMOS integration process flow are 0.75 and 0.05 cm
2/V
s, respectively. Threshold voltages (
V
t) are 1.14
V for nMOS and −1.89
V for pMOS. The voltage transfer curve of the CMOS inverter showed a gain of 16. Correct logic operation of integrated flexible NAND and NOR CMOS gates is also demonstrated. In addition, we show that the pMOS gate dielectric is likely failing after electrical stress. |
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| AbstractList | In this work we demonstrate a novel integration approach to fabricate CMOS circuits on plastic substrates (poly-ethylene naphthalate, PEN). We use pentacene and amorphous silicon (a-Si:H) thin-film transistors (TFTs) as p-channel and n-channel devices, respectively. The maximum processing temperature for n-channel TFTs is 180
°C and 120
°C for the p-channel TFTs. CMOS circuits demonstrated in this work include inverters, NAND, and NOR gates. Carrier mobilities for nMOS and pMOS after the CMOS integration process flow are 0.75 and 0.05 cm
2/V
s, respectively. Threshold voltages (
V
t) are 1.14
V for nMOS and −1.89
V for pMOS. The voltage transfer curve of the CMOS inverter showed a gain of 16. Correct logic operation of integrated flexible NAND and NOR CMOS gates is also demonstrated. In addition, we show that the pMOS gate dielectric is likely failing after electrical stress. |
| Author | Kaftanoglu, K. Allee, D.R. Gnade, B.E. Alshareef, H.N. Venugopal, S. Quevedo-Lopez, M.A. Gowrisanker, S. Krishna, R. |
| Author_xml | – sequence: 1 givenname: S. surname: Gowrisanker fullname: Gowrisanker, S. organization: Department of Materials Science and Engineering, University of Texas at Dallas, Richardson, TX 75080, United States – sequence: 2 givenname: M.A. surname: Quevedo-Lopez fullname: Quevedo-Lopez, M.A. email: mquevedo@utdallas.edu organization: Department of Materials Science and Engineering, University of Texas at Dallas, Richardson, TX 75080, United States – sequence: 3 givenname: H.N. surname: Alshareef fullname: Alshareef, H.N. organization: Department of Materials Science and Engineering, University of Texas at Dallas, Richardson, TX 75080, United States – sequence: 4 givenname: B.E. surname: Gnade fullname: Gnade, B.E. organization: Department of Materials Science and Engineering, University of Texas at Dallas, Richardson, TX 75080, United States – sequence: 5 givenname: S. surname: Venugopal fullname: Venugopal, S. organization: Flexible Display Center, Arizona State University, Tempe, AZ 85284, United States – sequence: 6 givenname: R. surname: Krishna fullname: Krishna, R. organization: Flexible Display Center, Arizona State University, Tempe, AZ 85284, United States – sequence: 7 givenname: K. surname: Kaftanoglu fullname: Kaftanoglu, K. organization: Flexible Display Center, Arizona State University, Tempe, AZ 85284, United States – sequence: 8 givenname: D.R. surname: Allee fullname: Allee, D.R. organization: Flexible Display Center, Arizona State University, Tempe, AZ 85284, United States |
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| Cites_doi | 10.1109/16.605476 10.1016/j.orgel.2009.05.003 10.1016/S0379-6779(98)00313-0 10.1002/(SICI)1521-4095(199803)10:5<365::AID-ADMA365>3.0.CO;2-U 10.1063/1.2956406 10.1109/TCE.1985.289880 10.1038/nnano.2008.296 10.1016/j.tsf.2008.10.060 10.1109/16.491245 10.1038/nmat1884 10.1109/TED.2007.899667 10.1063/1.3119636 10.1889/1.2759549 10.1109/FEDC.2008.4483882 10.1109/JPROC.2005.851509 10.1063/1.115873 10.1149/1.3046068 10.1063/1.2785852 10.1093/ietele/e91-c.12.1843 10.1021/ja901077a 10.1109/JPROC.2005.851497 10.1109/JDT.2006.890712 10.1889/1.2393030 10.1063/1.3077025 10.1063/1.2904968 10.1002/adma.200800629 10.1109/JPROC.2005.851525 |
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| Keywords | 84.30.−r 85.30.Tv NOR gate Hybrid CMOS 85.40.−e 73.61.Jc NAND gate Flexible electronics 72.80.Le 81.05.Gc Voltage threshold Amorphous material Electric stress Charge carrier mobility 85.40.-e n channel 84.30.-r Logic circuit Complementary MOS technology Silicon CMOS integrated circuits Inverter Pentacene NAND circuit PMOS technology NOR circuit p channel Flexible structure Amorphous hydrogenated material Thin film transistor Plastics NMOS technology Gain |
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| Snippet | In this work we demonstrate a novel integration approach to fabricate CMOS circuits on plastic substrates (poly-ethylene naphthalate, PEN). We use pentacene... |
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| SubjectTerms | Applied sciences Circuit properties Design. Technologies. Operation analysis. Testing Digital circuits Electric, optical and optoelectronic circuits Electronic circuits Electronic equipment and fabrication. Passive components, printed wiring boards, connectics Electronics Exact sciences and technology Flexible electronics Hybrid CMOS Integrated circuits NAND gate NOR gate Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Transistors |
| Title | A novel low temperature integration of hybrid CMOS devices on flexible substrates |
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