A novel low temperature integration of hybrid CMOS devices on flexible substrates

• Published in: Organic electronics Vol. 10; no. 7; pp. 1217 - 1222
• Main Authors: Gowrisanker, S., Quevedo-Lopez, M.A., Alshareef, H.N., Gnade, B.E., Venugopal, S., Krishna, R., Kaftanoglu, K., Allee, D.R.
• Format: Journal Article
• Language: English
• Published: Amsterdam Elsevier B.V 01.11.2009; Elsevier
• Subjects: Applied sciences; Circuit properties; Design. Technologies. Operation analysis. Testing; Digital circuits; Electric, optical and optoelectronic circuits; Electronic circuits; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics; Electronics; Exact sciences and technology; Flexible electronics; Hybrid CMOS; Integrated circuits; NAND gate; NOR gate; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Transistors; 84.30.−r; 85.30.Tv; NOR gate; Hybrid CMOS; 85.40.−e; 73.61.Jc; NAND gate; Flexible electronics; 72.80.Le; 81.05.Gc; Voltage threshold; Amorphous material; Electric stress; Charge carrier mobility; 85.40.-e; n channel; 84.30.-r; Logic circuit; Complementary MOS technology; Silicon; CMOS integrated circuits; Inverter; Pentacene; NAND circuit; PMOS technology; NOR circuit; p channel; Flexible structure; Amorphous hydrogenated material; Thin film transistor; Plastics; NMOS technology; Gain
• ISSN: 1566-1199; 1878-5530
• DOI: 10.1016/j.orgel.2009.06.012

In this work we demonstrate a novel integration approach to fabricate CMOS circuits on plastic substrates (poly-ethylene naphthalate, PEN). We use pentacene and amorphous silicon (a-Si:H) thin-film transistors (TFTs) as p-channel and n-channel devices, respectively. The maximum processing temperature for n-channel TFTs is 180 °C and 120 °C for the p-channel TFTs. CMOS circuits demonstrated in this work include inverters, NAND, and NOR gates. Carrier mobilities for nMOS and pMOS after the CMOS integration process flow are 0.75 and 0.05 cm 2/V s, respectively. Threshold voltages ( V t) are 1.14 V for nMOS and −1.89 V for pMOS. The voltage transfer curve of the CMOS inverter showed a gain of 16. Correct logic operation of integrated flexible NAND and NOR CMOS gates is also demonstrated. In addition, we show that the pMOS gate dielectric is likely failing after electrical stress.