A four channel time-to-digital converter ASIC with in-built calibration and SPI interface

A design of high resolution, wide dynamic range Time-to-Digital Converter (TDC) ASIC, implemented in 0.35µm commercial CMOS technology is presented. The ASIC features four channel TDC with an in-built calibration and Serial Peripheral Interconnect (SPI) slave interface. The TDC is based on the verni...

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Published inNuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment Vol. 737; pp. 117 - 121
Main Authors Hari Prasad, K., Sukhwani, Menka, Saxena, Pooja, Chandratre, V.B., Pithawa, C.K.
Format Journal Article
LanguageEnglish
Published Elsevier B.V 11.02.2014
Subjects
Accelerators
Aplication specific integrated circuit (ASIC)
Calibration
Channels
Converters
Dynamic range
High resolution
Nonlinearity
Oscillators
PVT
SPI
Time-to-digital conversion (TDC)
Vernier method
Vernier method
Time-to-digital conversion (TDC)
Calibration
SPI
Aplication specific integrated circuit (ASIC)
PVT
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Summary:A design of high resolution, wide dynamic range Time-to-Digital Converter (TDC) ASIC, implemented in 0.35µm commercial CMOS technology is presented. The ASIC features four channel TDC with an in-built calibration and Serial Peripheral Interconnect (SPI) slave interface. The TDC is based on the vernier ring oscillator method in order to achieve both high resolution and wide dynamic range. This TDC ASIC is tested and found to have resolution of 127ps (LSB), dynamic range of 1.8µs and precision (σ) of 74ps. The measured values of differential non-linearity (DNL) and integral non-linearity (INL) are 350ps and 300ps respectively.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0168-9002
1872-9576
DOI:10.1016/j.nima.2013.11.018