Reliability of Logic-in-Memory Circuits in Resistive Memory Arrays

• Published in: IEEE transactions on electron devices Vol. 67; no. 11; pp. 4611 - 4615
• Main Authors: Zanotti, Tommaso, Zambelli, Cristian, Puglisi, Francesco Maria, Milo, Valerio, Perez, Eduardo, Mahadevaiah, Mamathamba K., Ossorio, Oscar G., Wenger, Christian, Pavan, Paolo, Olivo, Piero, Ielmini, Daniele
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.11.2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Arrays; Back end of line (BEOL); Circuit reliability; Circuits; CMOS; Computer architecture; Computer networks; Device-to-device communication; Distributed processing; Energy consumption; full adder (FA); Integrated circuit reliability; Logic; logic-in-memory (LiM); Memory devices; Performance evaluation; Random access memory; Reliability analysis; Resistance; resistive random access memory (RRAM); smart IMPLY (SIMPLY); Transistors
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2020.3025271

Logic-in-memory (LiM) circuits based on resistive random access memory (RRAM) devices and the material implication logic are promising candidates for the development of low-power computing devices that could fulfill the growing demand of distributed computing systems. However, these circuits are affected by many reliability challenges that arise from device nonidealities (e.g., variability) and the characteristics of the employed circuit architecture. Thus, an accurate investigation of the variability at the array level is needed to evaluate the reliability and performance of such circuit architectures. In this work, we explore the reliability and performance of smart IMPLY (SIMPLY) (i.e., a recently proposed LiM architecture with improved reliability and performance) on two 4-kb RRAM arrays based on different resistive switching oxides integrated in the back end of line (BEOL) of the 0.25-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> BiCMOS process. We analyze the tradeoff between reliability and energy consumption of SIMPLY architecture by exploiting the results of an extensive array-level variability characterization of the two technologies. Finally, we study the worst case performance of a full adder implemented with the SIMPLY architecture and benchmark it on the analogous CMOS implementation.