Compact Modeling of Single-Event Latchup of Integrated CMOS Circuit

This paper presents a compact model of latchup considering design and process dependence. The new approach is more realistic and inspirited from the classical model. This model was used to confirm the single-event latchup (SEL) robustness of D-flip-flops (DFFs) used in Readout Circuit of Infrared-se...

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Bibliographic Details
Published inIEEE transactions on nuclear science Vol. 66; no. 7; pp. 1510 - 1515
Main Authors Al Youssef, A., Artola, L., Ducret, S., Hubert, G.
Format Journal Article
LanguageEnglish
Published New York IEEE 01.07.2019
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Bipolar transistors
Circuit design
CMOS
Compact modeling
complementary metal–oxide–semiconductor (CMOS)
Computer simulation
cross section
Dependence
design
Flip-flops
Infrared detectors
Integrated circuit modeling
Inverters
Modelling
Resistors
SEE prediction
Semiconductor device modeling
single-event latchup (SEL)
SPICE
spice simulation
technology computer-aided design (TCAD) simulation
Transistors
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Summary:This paper presents a compact model of latchup considering design and process dependence. The new approach is more realistic and inspirited from the classical model. This model was used to confirm the single-event latchup (SEL) robustness of D-flip-flops (DFFs) used in Readout Circuit of Infrared-sensors developed by Sofradir. SEL cross sections are presented by the mean of the Monte Carlo tool MUSCA SEP3 in order to validate the new latchup modeling approach.
ISSN:0018-9499
1558-1578
DOI:10.1109/TNS.2019.2920629