Majority Logic Decoding Under Data-Dependent Logic Gate Failures

A majority logic decoder made of unreliable logic gates, whose failures are transient and data-dependent, is analyzed. Based on a combinatorial representation of fault configurations a closed-form expression for the average bit error rate for a one-step majority logic decoder is derived, for a regul...

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Bibliographic Details
Published inIEEE transactions on information theory Vol. 63; no. 10; pp. 6295 - 6306
Main Authors Brkic, Srdan, Ivanis, Predrag, Vasic, Bane
Format Journal Article
LanguageEnglish
Published New York IEEE 01.10.2017
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Binary system
Bit error rate
Circuit faults
Codes
Combinatorial analysis
Data-dependence
Decoding
Error correcting codes
Failure analysis
faulty hardware
Iterative decoding
LDPC codes
Logic circuits
Logic gates
majority logic decoding
Mathematical models
Noise measurement
probabilistic gate-output switching model
Reliability
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Summary:A majority logic decoder made of unreliable logic gates, whose failures are transient and data-dependent, is analyzed. Based on a combinatorial representation of fault configurations a closed-form expression for the average bit error rate for a one-step majority logic decoder is derived, for a regular low-density parity-check (LDPC) code ensemble and the proposed failure model. The presented analysis framework is then used to establish bounds on the one-step majority logic decoder performance under the simplified probabilistic gate-output switching model. Based on the expander property of Tanner graphs of LDPC codes, it is proven that a version of the faulty parallel bit-flipping decoder can correct a fixed fraction of channel errors in the presence of data-dependent gate failures. The results are illustrated with numerical examples of finite geometry codes.
ISSN:0018-9448
1557-9654
DOI:10.1109/TIT.2017.2741466