A 65 nm Cryptographic Processor for High Speed Pairing Computation

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 23; no. 4; pp. 692 - 701
• Main Authors: Jun Han, Yang Li, Zhiyi Yu, Xiaoyang Zeng
• Format: Journal Article
• Language: English
• Published: IEEE 01.04.2015
• Subjects: Adders; Cryptographic pairings; Cryptography; Delays; Hardware; high speed processor; Montgomery modular multiplication; Optimization; Pipelines; montgomery modular multiplication; high speed processor; Cryptographic pairings
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2014.2316514

Pairings are attractive and competitive cryptographic primitives for establishing various novel and powerful information security schemes. This paper presents a flexible and high-performance processor for cryptographic pairings over pairing-friendly curves at high security levels. In this design, hardware for F p2 arithmetic is optimized to accelerate the pairing computation, and especially a combined modular multiplier, which implements (AB + CD) based on Montgomery method, is proposed. This combined multiplier has the data path delay close to that of a single multiplier implementing (AB) but saves 20% area cost compared with two single multipliers. The Design I of the proposed processor is the first fabricated chip for pairing cryptography. An improved version, Design II, is implemented using TSMC 65-nm CMOS technology and achieves the working frequency of 633 MHz after placing and routing. As demonstrated, the optimal ate pairings of 126- and 128-bit security can be computed by Design II in 0.521 and 0.554 ms, respectively. These results outperform the hardware implementations reported by previous works.