Improvement of Post-Fault Performance of a Cascaded H-bridge Multilevel Inverter

This paper is focused on improving the post-fault performance of cascaded H-bridge multilevel inverters by decreasing the common-mode voltage. First, an algorithm is proposed to determine the optimal post-fault state among all possible states, which have the same maximum available voltage. Furthermo...

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Bibliographic Details
Published inIEEE transactions on industrial electronics (1982) Vol. 64; no. 4; pp. 2779 - 2788
Main Authors Ouni, Saeed, Reza Zolghadri, Mohammad, Khodabandeh, Masih, Shahbazi, Mahmoud, Rodriguez, Jose, Oraee, Hashem, Lezana, Pablo, Ulloa Schmeisser, Andres
Format Journal Article
LanguageEnglish
Published New York IEEE 01.04.2017
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Cascaded H-bridge multilevel inverter
Circuit faults
common-mode voltage
Computer simulation
Control systems
Electric potential
Fault tolerance
Fault tolerant systems
fault-tolerant inverter
Inverters
Voltage control
Windings
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Summary:This paper is focused on improving the post-fault performance of cascaded H-bridge multilevel inverters by decreasing the common-mode voltage. First, an algorithm is proposed to determine the optimal post-fault state among all possible states, which have the same maximum available voltage. Furthermore, a modified technique is proposed to calculate the references of inverter phase voltages under faulty conditions. This technique leads to a decrease in the common-mode voltage when the required output voltage is less than its maximum value. These solutions are mutually employed in the post-fault control system. Simulation and experimental results confirm the effectiveness of the proposed solutions in comparison with the existing methods in different cases.
ISSN:0278-0046
1557-9948
DOI:10.1109/TIE.2016.2632058