A low-power fast tag comparator by modifying charging scheme of wide fan-in dynamic OR gates

• Published in: Integration (Amsterdam) Vol. 52; pp. 129 - 141
• Main Authors: Nasserian, Mahshid, Kafi-Kangi, Mohammad, Maymandi-Nejad, Mohammad, Moradi, Farshad
• Format: Journal Article
• Language: English
• Published: Elsevier B.V 01.01.2016
• Subjects: Circuit design; Circuits; Comparators; Delay; Dynamic logic; Dynamics; Gates (circuits); Power consumption; Power-delay product; Reduced power; Simulation; Wide fan-in; Reduced power; Dynamic logic; Wide fan-in; Power-delay product
• ISSN: 0167-9260; 1872-7522
• DOI: 10.1016/j.vlsi.2015.09.004

In this paper, a new charging scheme for reducing the power consumption of dynamic circuits is presented. The proposed technique is suitable for large fan-in gates where the dynamic node discharges frequently. Simulation results demonstrate that the proposed method is efficiently controlling the internal voltage swing and hence decreasing the power consumption of the wide fan-in OR gate without sacrificing other circuit parameters such as gate speed, area or noise immunity. The power-delay product of a simulated 8-input OR gate is reduced by 46%, compared to its conventional dynamic counterpart in the 90nm CMOS technology. Another important benefit of the proposed approach is 99X reduction in power dissipation of the gate load by limiting its switching activity. Furthermore, the delay of the proposed circuit experiences only 0.94% variation over 10% fluctuation in the threshold voltages of all transistors for a 32-bit OR gate. Using the proposed technique, a 40-bit tag comparator is simulated at 1GHz clock frequency. The power consumption of the designed circuit is as low as 1.987µW/MHz, while the delay and unity noise gain (UNG) of the circuit are 244ps and 499mV, respectively. •A new technique called MCSD is presented for reducing the power consumption of wide fan-in dynamic OR circuits.•It has shown that in modern technology nodes using the MCSD technique, the power consumption of the OR gates can be effectively reduced without sacrificing other circuit parameters.•An important benefit of the proposed approach is 98.7X reduction in power consumption of the gate load by limiting its switching activity.•Using the proposed technique, a 40-bit Tag Compotator is designed that its power-delay product is reduced approximately by 49.4%.