Investigation of the Scalability of Emerging Nanotube Junctionless FETs Using an Intrinsic Pocket

• Published in: IEEE journal of the Electron Devices Society Vol. 7; pp. 888 - 896
• Main Authors: Jain, Aakash Kumar, Singh, Jaspreet, Kumar, Mamidala Jagadesh
• Format: Journal Article
• Language: English
• Published: New York IEEE 2019; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Band-to-band tunneling (BTBT); Computer architecture; Doping; Drain induced barrier lowering (DIBL); Field effect transistors; Gate induced drain leakage (GIDL); Junctionless accumulation mode FET (JAMFET); Leakage current; Logic gates; Nanotube JAMFET (NT JAMFET); Nanotube Junctionless FET (NT JLFET); Nanotubes; parasitic bipolar junction transistor (BJT); Performance degradation; Scalability; Semiconductor devices; Semiconductor process modeling; Transistors; Tunneling; Work functions
• ISSN: 2168-6734; 2168-6734
• DOI: 10.1109/JEDS.2019.2935319

The detrimental lateral band-to-band tunneling (L-BTBT) governing the OFF-state performance of the junctionless (JL) FETs is more pronounced in emerging Nanotube (NT) transistor architectures. This restricts the scaling of NT JLFETs irrespective of their ultimate electrostatic gate control due to additional core gate. Therefore, in this paper, we propose a symmetric intrinsic pocketed Pi-NT JLFET which has narrow intrinsic pockets on both sides of the channel region leading to a diminished L-BTBT induced lateral parasitic BJT action in the emerging NT JLFETs. Using calibrated 3-D simulations, we demonstrate that the incorporation of an intrinsic pocket decreases the OFF-state current by around 2 orders of magnitude in the Pi-NT JLFET for a gate length of 20 nm, leading to a significant ON-state to OFF-state current ratio (I ON /I OFF ) of 10 8 . Furthermore, we also show an improvement in the performance of the emerging NT junctionless accumulation mode (JAM) FETs which exhibits a degraded performance compared to NT JLFETs due to enhanced L-BTBT irrespective of their higher ON-state current. The inclusion of the intrinsic pockets in NT JAMFET (Pi-NT JAMFET) reduces the L-BTBT originated OFF-state by 3 orders of magnitude for a gate length of 20 nm leading to an impressive (I ON /I OFF ) ratio of 10 8 . Moreover, the proposed Pi-NT JLFET and Pi-NT JAMFET exhibit an impressive (I ON /I OFF ) ratio of ~ 10 8 and 10 6 , respectively, with more than 4 orders of remarkable reduction in the leakage current even when the gate length is scaled to 10 nm. Additionally, the proposed architectures exhibit lower sensitivity to the gate length modulation unlike their conventional counterpart. The Pi-NT transistors exhibit superior immunity against the short channel effects of threshold-voltage roll-off due to the reduced electrostatic source/channel-to-drain coupling. Furthermore, we show that incorporating gate engineering of the dual-material gate (DMG) further enhances the performance of the Pi-NT transistor. The DMG-Pi-NT transistors exhibit an enhanced (I ON /I OFF ) ratio ~ 10 11 achievable with the proper tuning of the dual metal gate work functions. Thus, our proposed device architecture enhances the scalability of the NT JLFETs and NT JAMFETs for realizing them in the future technology nodes.