A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology
A high-performance low-power 153 Mb SRAM is developed in 45 nm high-k Metal Gate technology. Dynamic SRAM PMOS forward-body-bias (FBB) and Active-Controlled SRAM VCC in Sleep are integrated in the design to lower Active-VCCmin and Standby Leakage, respectively. FBB improves the Active-VCCmin by up t...
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Published in | IEEE journal of solid-state circuits Vol. 44; no. 1; pp. 148 - 154 |
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Main Authors | , , , , , , , , , |
Format | Journal Article Conference Proceeding |
Language | English |
Published |
New York, NY
IEEE
01.01.2009
Institute of Electrical and Electronics Engineers The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subjects | |
Online Access | Get full text |
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Summary: | A high-performance low-power 153 Mb SRAM is developed in 45 nm high-k Metal Gate technology. Dynamic SRAM PMOS forward-body-bias (FBB) and Active-Controlled SRAM VCC in Sleep are integrated in the design to lower Active-VCCmin and Standby Leakage, respectively. FBB improves the Active-VCCmin by up to 75 mV, and Active-Controlled SRAM VCC distribution tightened by 100 mV, both of which result in further power reduction. A 0.346 mum 2 6T-SRAM bit-cell is used which is optimized for VCCmin, performance, leakage and area. The design operates at high-speed over a wide voltage range, and has a maximum frequency of 3.8 GHz at 1.1 V. The 16 KB Subarray was also used as the building block in on-die 6 MB Cache for Intel Core 2 Duo CPU in 45 nm technology. |
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Bibliography: | ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 23 |
ISSN: | 0018-9200 1558-173X |
DOI: | 10.1109/JSSC.2008.2007151 |