A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology

• Published in: IEEE journal of solid-state circuits Vol. 44; no. 1; pp. 148 - 154
• Main Authors: Hamzaoglu, F., Zhang, K., Yih Wang, Ahn, H.J., Bhattacharya, U., Zhanping Chen, Yong-Gee Ng, Pavlov, A., Smits, K., Bohr, M.
• Format: Journal Article Conference Proceeding
• Language: English
• Published: New York, NY IEEE 01.01.2009; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Blocking; CMOS; CMOS technology; Contacts; Design. Technologies. Operation analysis. Testing; Electronics; Energy consumption; Exact sciences and technology; Forward-body-bias; Gates; High K dielectric materials; High speed; High-K gate dielectrics; Integrated circuits; Integrated circuits by function (including memories and processors); Leakage; leakage reduction; Logic circuits; low-power; Random access memory; Reduction; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Sleep; sleep transistor; Stability; Static random access memory; Static-random-access-memory (SRAM); Transistors; Very large scale integration; Voltage; Performance evaluation; High performance; Die; Static random access memory; Processor; low-power; Cache memory; Random access memory; PMOS technology; high-speed; Transistor; leakage reduction; Optimization; Overvoltage; Static-random-access-memory (SRAM); Complementary MOS technology; Integrated circuit; Dynamic stability; Integrated design; High k dielectric; Forward-body-bias; Low-power electronics; sleep transistor
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2008.2007151

A high-performance low-power 153 Mb SRAM is developed in 45 nm high-k Metal Gate technology. Dynamic SRAM PMOS forward-body-bias (FBB) and Active-Controlled SRAM VCC in Sleep are integrated in the design to lower Active-VCCmin and Standby Leakage, respectively. FBB improves the Active-VCCmin by up to 75 mV, and Active-Controlled SRAM VCC distribution tightened by 100 mV, both of which result in further power reduction. A 0.346 mum 2 6T-SRAM bit-cell is used which is optimized for VCCmin, performance, leakage and area. The design operates at high-speed over a wide voltage range, and has a maximum frequency of 3.8 GHz at 1.1 V. The 16 KB Subarray was also used as the building block in on-die 6 MB Cache for Intel Core 2 Duo CPU in 45 nm technology.