iVisual: An Intelligent Visual Sensor SoC With 2790 fps CMOS Image Sensor and 205 GOPS/W Vision Processor

• Published in: IEEE journal of solid-state circuits Vol. 44; no. 1; pp. 127 - 135
• Main Authors: CHENG, Chih-Chi, LIN, Chia-Hua, LI, Chung-Te, CHEN, Liang-Gee
• Format: Journal Article Conference Proceeding
• Language: English
• Published: New York, NY IEEE 01.01.2009; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Clocks; CMOS; CMOS image sensors; Design. Technologies. Operation analysis. Testing; Electronics; Energy consumption; Exact sciences and technology; GOPS; Hardware; Image sensors; Imaging devices; Integrated circuits; Integrated circuits by function (including memories and processors); Intelligent sensors; intelligent visual sensor; Microprocessors; Process design; Processor arrays; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Sensor arrays; Sensors; Signal processing algorithms; SIMD; single-instruction multiple-data; Synchronism; Throughput; video analysis; Vision; vision processor; Visual; Performance evaluation; Die; Static random access memory; intelligent visual sensor; Array processor; Random access memory; SIMD computer; CMOS image sensors; vision processor; System on a chip; GOPS; SIMD; Synchronization; video analysis; Mismatching; Storage access; Intelligent sensors; Data flow; Image analysis; Power consumption; Integrated circuit; single-instruction multiple-data
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2008.2007158

iVisual, an intelligent visual sensor SoC integrating 2790 fps CMOS image sensor and 76.8 GOPS, 374 mW vision processor, is implemented on a 7.5 mm × 9.4 mm die in a UMC 0.18 mum CMOS Image Sensor process. Light-in, answer-out SoC architecture is adopted to avoid possible privacy problems. A feature processor is designed to eliminate the dataflow mismatch between processor array and scalar processor to increase 36% of average throughput. To increase hardware utilization, an inter-processor synchronization scheme is adopted to increase 23% of average throughput. Memory access is reduced by 94% to save 726 mW of power consumption. A bitplane-based single port memory structure is adopted to reduce SRAM area. The 205 GOPS/W power efficiency and 1.16 GOPS/mm 2 area efficiency are therefore achieved by use of the proposed techniques.