Multilevel optimization in the design of a high-performance GaAs microcomputer

Multilevel optimization in the design of an instruction cache for a high-performance GaAs microprocessor is discussed. The performance of the system is maximized by concurrently considering the interrelationships of (1) the time of flight of signals across the multichip module on which the processor...

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Bibliographic Details
Published inIEEE journal of solid-state circuits Vol. 26; no. 5; pp. 763 - 767
Main Authors Olukotun, O.A., Brown, R.B., Lomax, R.J., Mudge, T.N., Sakallah, K.A.
Format Journal Article
LanguageEnglish
Published New York, NY IEEE 01.05.1991
Institute of Electrical and Electronics Engineers
Subjects
Applied sciences
Clocks
Design automation
Design optimization
Electronics
Exact sciences and technology
Gallium arsenide
Microcomputers
Microprocessors
Multichip modules
Performance gain
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Signal processing
Synchronization
Gallium Arsenides
High performance
Subsystem
Microprocessor
Performance
Optimization
Microcomputer
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Summary:Multilevel optimization in the design of an instruction cache for a high-performance GaAs microprocessor is discussed. The performance of the system is maximized by concurrently considering the interrelationships of (1) the time of flight of signals across the multichip module on which the processor and cache chips are mounted, (2) the clocking scheme that synchronizes these signals, and (3) the size of the cache. These three design issues are normally considered independently because they arise in different abstraction levels. Design automation tools developed to facilitate this multilevel optimization are described. This process, applied to various subsystems, has been used to gain substantial performance improvement in the GaAs microcomputer.< >
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0018-9200
1558-173X
DOI:10.1109/4.78246