Surface Engineering of SiC through Nanogrinding and CMP

Processing silicon carbide (SiC) wafers to achieve an epi-ready quality finish typically requires many lapping and a very long chemical mechanical polishing (CMP) steps. In this paper, we report the thinning down of 6” SiC wafers to sub-nanometer surface finish in less than two hours. Three process...

Full description

Saved in:
Bibliographic Details
Published inMaterials science forum Vol. 924; pp. 539 - 542
Main Authors Gibson, A., Walters, A., Shindo, T., Vacassy, Robert, Titov, A.
Format Journal Article
LanguageEnglish
Published Pfaffikon Trans Tech Publications Ltd 05.06.2018
Subjects
Online AccessGet full text

Cover

Loading…
More Information
Summary:Processing silicon carbide (SiC) wafers to achieve an epi-ready quality finish typically requires many lapping and a very long chemical mechanical polishing (CMP) steps. In this paper, we report the thinning down of 6” SiC wafers to sub-nanometer surface finish in less than two hours. Three process steps (rough grinding, nanogrinding and CMP) are involved. Rough grinding thins down the wafer with fast feed rate and maintain excellent flatness. Nanogrinding allows the surface finish to improve down to a few nanometers. The last CMP step provides high planarization efficiency. Overall the throughput of SiC processing is substantially increased over current market solutions.
Bibliography:Selected, peer reviewed papers from the 2017 International Conference on Silicon Carbide and Related Materials (ICSCRM 2017), September 17-22, 2017, Washington, DC, USA
ISSN:0255-5476
1662-9752
1662-9752
DOI:10.4028/www.scientific.net/MSF.924.539