FRESH: A New Test Result Extraction Scheme for Fast TSV Tests
Three-dimensional integrated circuits (3-D ICs) are considered to meet the performance needs of future ICs. The core components of 3-D ICs are through-silicon vias (TSVs), which should pass appropriate prebond and post-bond tests in 3-D IC fabrication processes. The test inputs must be injected into...
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Published in | IEEE transactions on computer-aided design of integrated circuits and systems Vol. 36; no. 2; pp. 336 - 345 |
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Main Authors | , , |
Format | Journal Article |
Language | English |
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IEEE
01.02.2017
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Abstract | Three-dimensional integrated circuits (3-D ICs) are considered to meet the performance needs of future ICs. The core components of 3-D ICs are through-silicon vias (TSVs), which should pass appropriate prebond and post-bond tests in 3-D IC fabrication processes. The test inputs must be injected into the TSVs, and the test results must be extracted. This paper proposes a new test result extraction scheme [fast result extraction by selective shift-out (FRESH)] for prebond and post-bond TSV testing. With additional hardware, the proposed scheme remarkably reduces the TSV test time. FRESH avoids unnecessary test result extraction when the number of faulty TSVs in the TSV set is 0 or exceeds the number of TSV redundancies in the set. These early fault analyses are executed in the checkers of TSV groups. The experimental results show that the proposed scheme can reduce the result extraction time in practical environments. |
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AbstractList | Three-dimensional integrated circuits (3-D ICs) are considered to meet the performance needs of future ICs. The core components of 3-D ICs are through-silicon vias (TSVs), which should pass appropriate prebond and post-bond tests in 3-D IC fabrication processes. The test inputs must be injected into the TSVs, and the test results must be extracted. This paper proposes a new test result extraction scheme [fast result extraction by selective shift-out (FRESH)] for prebond and post-bond TSV testing. With additional hardware, the proposed scheme remarkably reduces the TSV test time. FRESH avoids unnecessary test result extraction when the number of faulty TSVs in the TSV set is 0 or exceeds the number of TSV redundancies in the set. These early fault analyses are executed in the checkers of TSV groups. The experimental results show that the proposed scheme can reduce the result extraction time in practical environments. |
Author | Jaeseok Park Hyunyul Lim Sungho Kang |
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Cites_doi | 10.1109/TVLSI.2013.2293192 10.1109/TVLSI.2011.2107924 10.1109/TCPMT.2011.2166961 10.1109/TCAD.2012.2228742 10.1109/JSSC.2009.2034408 10.1109/TCSI.2014.2354752 10.1145/2228360.2228545 10.1109/TCAD.2010.2051732 10.1109/TCAD.2011.2160177 10.1109/VTS.2010.5469559 10.1109/TVLSI.2014.2306951 10.1109/VTS.2014.6818771 10.1109/TEST.2011.6139179 10.1109/VLSISoC.2011.6081648 10.1109/ASPDAC.2012.6165052 10.1109/VTS.2011.5783749 |
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SubjectTerms | Circuit faults Hardware Maintenance engineering post-bond test prebond test test result extraction Testing Three-dimensional displays Three-dimensional integrated circuit (3-D IC) through-silicon via (TVS) repair Through-silicon vias TSV test |
Title | FRESH: A New Test Result Extraction Scheme for Fast TSV Tests |
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