Transparent code authentication at the processor level

• Published in: IET computers & digital techniques Vol. 3; no. 4; pp. 354 - 372
• Main Authors: DURAHIM, A. O, SAVAS, E, SUNAR, B, PEDERSEN, T. B, KOCABAS, O
• Format: Journal Article
• Language: English
• Published: Stevenage Institution of Engineering and Technology 01.07.2009; John Wiley & Sons, Inc
• Subjects: Applied sciences; Authentication; Computer programs; Design. Technologies. Operation analysis. Testing; Digital techniques; Electronics; Encryption; Exact sciences and technology; Hardware; Integrated circuits; Integrated circuits by function (including memories and processors); Microprocessors; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Software; Weight reduction; Performance evaluation; Computer virus; Processor; Cache memory; Coding; Authentication; Integrated circuit; Intellectual property; Software; Storage access
• ISSN: 1751-8601; 1751-861X
• DOI: 10.1049/iet-cdt.2007.0122

The authors present a lightweight authentication mechanism that verifies the authenticity of code and thereby addresses the virus and malicious code problems at the hardware level eliminating the need for trusted extensions in the operating system. The technique proposed tightly integrates the authentication mechanism into the processor core. The authentication latency is hidden behind the memory access latency, thereby allowing seamless on-the-fly authentication of instructions. In addition, the proposed authentication method supports seamless encryption of code (and static data). Consequently, while providing the software users with assurance for authenticity of programs executing on their hardware, the proposed technique also protects the software manufacturers' intellectual property through encryption. The performance analysis shows that, under mild assumptions, the presented technique introduces negligible overhead for even moderate cache sizes.