High-speed, fixed-latency serial links with Xilinx FPGAs

High-speed, fixed-latency serial links find application in distributed data acquisition and control systems, such as the timing trigger and control （TTC） system for high energy physics experiments. However, most high-speed serial transceivers do not keep the same chip latency after each power-up or...

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Bibliographic Details
Published inFrontiers of information technology & electronic engineering Vol. 15; no. 2; pp. 153 - 160
Main Authors Liu, Xue, Deng, Qing-xu, Hou, Bo-ning, Wang, Ze-ke
Format Journal Article
LanguageEnglish
Published Berlin/Heidelberg Springer Berlin Heidelberg 01.02.2014
Springer Nature B.V
Subjects
Circuits
Clock generators
Clocks
Communications Engineering
Computer Hardware
Computer Science
Computer Systems Organization and Communication Networks
Data acquisition
Electrical Engineering
Electronics and Microelectronics
Field programmable gate arrays
High speed
Instrumentation
Networks
Phase locked loops
Phase shift
Transceivers
Fixed-latency
Trigger system
Field programmable gate array (FPGA)
TN79
Data acquisition circuit
Serial link
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Summary:High-speed, fixed-latency serial links find application in distributed data acquisition and control systems, such as the timing trigger and control （TTC） system for high energy physics experiments. However, most high-speed serial transceivers do not keep the same chip latency after each power-up or reset, as there is no deterministic phase relationship between the transmitted and received clocks after each power-up. In this paper, we propose a fixed-latency serial link based on high-speed transceivers embedded in Xilinx field programmable gate arrays （FPGAs）. First, we modify the configuration and clock distribution of the transceiver to eliminate the phase difference between the clock domains in the transmitter/receiver. Second, we use the internal alignment circuit of the transceiver and a digital clock manager （DCM）/phase-locked loop （PLL） based clock generator to eliminate the phase difference between the clock domains in the transmitter and receiver. The test results of the link latency are shown. Compared with existing solutions, our design not only implements fixed chip latency, but also reduces the average system lock time.
Bibliography:Data acquisition circuit, Fixed-latency, Field programmable gate array （FPGA）, Serial link, Trigger system
High-speed, fixed-latency serial links find application in distributed data acquisition and control systems, such as the timing trigger and control （TTC） system for high energy physics experiments. However, most high-speed serial transceivers do not keep the same chip latency after each power-up or reset, as there is no deterministic phase relationship between the transmitted and received clocks after each power-up. In this paper, we propose a fixed-latency serial link based on high-speed transceivers embedded in Xilinx field programmable gate arrays （FPGAs）. First, we modify the configuration and clock distribution of the transceiver to eliminate the phase difference between the clock domains in the transmitter/receiver. Second, we use the internal alignment circuit of the transceiver and a digital clock manager （DCM）/phase-locked loop （PLL） based clock generator to eliminate the phase difference between the clock domains in the transmitter and receiver. The test results of the link latency are shown. Compared with existing solutions, our design not only implements fixed chip latency, but also reduces the average system lock time.
ISSN:1869-1951
2095-9184
1869-196X
2095-9230
DOI:10.1631/jzus.C1300249