Can silicon FinFETs satisfy ITRS projections for high performance 10 nm devices?

We utilize a fully self-consistent quantum mechanical simulator based on CBR method to optimize 10 nm FinFET devices to meet ITRS projections for High Performance (HP) logic technology devices. Fin width, gate oxide thickness, and doping profiles are chosen to reflect realistic values. We find that...

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Bibliographic Details
Published inJournal of computational electronics Vol. 7; no. 3; pp. 284 - 287
Main Authors Khan, H., Mamaluy, D., Vasileska, D.
Format Journal Article Conference Proceeding
LanguageEnglish
Published Boston Springer US 01.09.2008
Kluwer Academic Publishers
Springer Nature B.V
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Summary:We utilize a fully self-consistent quantum mechanical simulator based on CBR method to optimize 10 nm FinFET devices to meet ITRS projections for High Performance (HP) logic technology devices. Fin width, gate oxide thickness, and doping profiles are chosen to reflect realistic values. We find that the device on-current approaching the value projected by ITRS for HP devices can be obtained using unstrained conventional (Si) channel. Our simulation results also show that quantum nature of transport in ultra small devices significantly enhances the intrinsic switching speed of the device. In addition, small signal analysis has been performed. Sensitivity of device performance to the process variation at room temperature has also been investigated.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:1569-8025
1572-8137
DOI:10.1007/s10825-008-0194-6