Copper voids improvement for the copper dual damascene interconnection process

• Published in: The Journal of physics and chemistry of solids Vol. 69; no. 2; pp. 566 - 571
• Main Authors: Wang, T.C., Wang, Y.L., Hsieh, T.E., Chang, S.C., Cheng, Y.L.
• Format: Journal Article Conference Proceeding
• Language: English
• Published: Oxford Elsevier Ltd 01.02.2008; Elsevier
• Subjects: A. Semiconductors; A. Thin films; Applied sciences; D. Defects; D. Electrical properties; Electronics; Exact sciences and technology; Microelectronic fabrication (materials and surfaces technology); Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; A. Thin films; D. Defects; A. Semiconductors; D. Electrical properties; Grain size; Mechanical polishing; Semiconductor materials; Chemical polishing; Cavitation; Damascene process; Thin film; Microelectronic fabrication; Transmission electron microscopy; Corrosion; Defect; Electrodeposition; Copper
• ISSN: 0022-3697; 1879-2553
• DOI: 10.1016/j.jpcs.2007.07.119

The mechanism of copper (Cu) voids formation from electro-chemical plating (ECP) followed by Cu chemical mechanical polishing (CMP) are studied in Cu dual-damascene interconnection. The formation of Cu voids at metal lines is the main problem that causes not only the failure of via-induced metal-island corrosion but also yield loss. The galvanic theory and Cu lifting mechanism are proposed to explain the dependence of Cu-void performance on the Cu grain size and the benzotriazole (BTA, C 6H 5N 3) flow rates. In the integration process of Cu interconnects, it is found that the smaller Cu grain size in ECP conditions and less BTA flow rate in CMP processes cannot only reduce the number of Cu voids but also improve the wafer yield.