Virtual synaptic interconnect using an asynchronous network-on-chip

• Published in: 2008 IEEE International Joint Conference on Neural Networks (IEEE World Congress on Computational Intelligence) Vol. 10; pp. 2727 - 2734
• Main Authors: Rast, A.D., Shufan Yang, Khan, M., Furber, S.B.
• Format: Conference Proceeding Journal Article
• Language: English
• Published: IEEE 01.06.2008
• Subjects: Artificial neural networks; Biological system modeling; Computational modeling; Hardware; Neurons; Program processors; SDRAM
• ISBN: 1424418208; 9781424418206; 9781424432196; 1424432197
• ISSN: 2161-4393; 1522-4899; 2161-4407
• DOI: 10.1109/IJCNN.2008.4634181

Given the limited current understanding of the neural model of computation, hardware neural network architectures that impose a specific relationship between physical connectivity and model topology are likely to be overly restrictive. Here we introduce, in the SpiNNaker chip, an alternative approach: a mappable virtual topology using an asynchronous network-on-chip (NoC) that decouples the ldquologicalrdquo connectivity map from the physical wiring. Borrowing the established digital RAM model for synapses, we develop a concurrent memory access channel optimised for neural processing that allows each processing node to perform its own synaptic updates as if the synapses were local to the node. The highly concurrent nature of interconnect access, however, requires careful design of intermediate buffering and arbitration. We show here how a locally buffered, one-transaction-per-node model with multiple synapse updates per transaction enables the local node to offload continuous burst traffic from the NoC, allowing for a hardware-efficient design that supports biologically realistic speeds. The design not only presents a flexible model for neural connectivity but also suggests an ideal form for general-purpose high-performance on-chip interconnect.