Impact of stress-induced backflow on full-chip electromigration risk assessment

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 25; no. 6; pp. 1038 - 1046
• Main Authors: Haznedar, H., Gall, M., Zolotov, V., Pon Sung Ku, Oh, C., Panda, R.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.06.2006; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Design automation; Electromigration; Equations; integrated circuit reliability; Linear systems; Microprocessor chips; Risk assessment; Risk management; Stress; Studies; Topology; Wire; Wiring
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2005.855941

This paper presents a linear system formulation for evaluating full-chip electromigration (EM) risk in general (straight line, tree, and mesh) wiring topologies, considering stress-induced backflow of metal ions. The system of equations is based on stress gradients and mass displacements in wire segments as variables, and is formulated for efficient implementation in computer-aided design (CAD) tools for designing high-performance microprocessor chips involving large databases. Derived from a well-known hydrostatic stress model in tree interconnects (J. Appl. Phys., vol. 47, no. 4, p. 1203, 1976; IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 18, no. 5, p. 576, 1999; Microelectron. Reliab., vol. 39, no. 11, p. 1667, 1999), the system is readily modified for evaluating EM risk in mesh topologies. The authors demonstrated a significant increase in the predicted lifetime of a high-performance microprocessor with the application of the proposed method to filter out risk-free structures from subsequent statistical EM risk calculations