Charge-injection photogate pixel fabricated in CMOS silicon-on-insulator technology

• Published in: International journal of circuit theory and applications Vol. 37; no. 2; pp. 179 - 192
• Main Authors: Durini, Daniel, Brockherde, Werner, Hosticka, Bedrich J.
• Format: Journal Article
• Language: English
• Published: Chichester, UK John Wiley & Sons, Ltd 01.03.2009
• Subjects: charge-injection photogate; CMOS imaging; enhanced NIR imaging; peak detect-and-hold circuit; SOI; standard CMOS processes; time-compression amplification
• ISSN: 0098-9886; 1097-007X
• DOI: 10.1002/cta.538

Concept, theoretical analysis, and experimental results obtained from a charge‐injection photogate (CI‐PG) pixel detector fabricated in CMOS silicon‐on‐insulator (SOI) technology are presented. The charge collected in the photodetector during a certain charge collection (integration) time is injected into the substrate for readout. This readout principle presents a huge internal photocurrent amplification (∼104) taking place in the photodetector, obtained through the ‘time‐compression’ approach. Here, the readout circuitry is fabricated on highly doped, 200 nm thick, SOI film, while the photogate detector is fabricated on higher resistivity handle‐wafer. The latter, together with the 30 V biasing possibilities, enhances the quantum efficiency of the pixel, especially for irradiations with wavelengths in the near‐infra‐red part of the spectra. Copyright © 2008 John Wiley & Sons, Ltd.